领域：高端装备制造产业 学校：南京大学职称：教授
现代纠错码设计与实现；高速有线和无线通信系统；生物医学信号处理系统；深度学习算法及硬件加速；低功耗设计方法学；容错集成电路设计；硬件安全与集成电路设计
...
具体了解该专家信息，请致电：027-87555799 邮箱 haizhi@uipplus.com
Z. Wang and J. Ma “Fast Interpolation Architecture for Soft-Decision Decoding of Reed-Solomon Codes”, in IEEE Trans. on VLSI Systems, vol. 14, no. 9, pp. 937-950, Sep. 2006 (IEEE VLSI Transactions Best Paper Award in 2007) .
Z. Wang and Z. Cui, “Low Complexity, High Speed Decoder Design for Quasi-Cyclic Low Density Parity Check Codes”, in IEEE Trans. on VLSI Systems, vol. 15, no. 1, Jan. 2007 (Top 4 most downloaded papers in IEEE Trans. on VLSI Systems in 2007).
Z. Wang and Z. Cui, “Area-Efficient Parallel Decoder Architectures for QC-LDPC Codes”, in IEEE Trans. on VLSI Systems in Apr. 2007.
Z. Wang, “High-Speed Recursion Architecture for Turbo/MAP Decoders”, in IEEE Trans. on VLSI Systems in Apr. 2007.
Z. Wang and Q. Li, “Very Low Complexity Hardware Interleaver for Turbo Decoding,” in IEEE Trans. on Circuits and Systems: II, Sep. 2007.
J. Ma, A. Vardy, and Z. Wang, “Low-latency Factorization Architecture for Algebraic Soft-Decision Decoding of Reed-Solomon Codes,” in IEEE Trans. on VLSI Systems, Nov. 2007.
Z. Cui and Z. Wang “High Speed Layered LDPC Decoder Architecture for QC-LDPC Codes,” in IEEE Trans. on VLSI Systems in Apr. 2009 (Top 8 most downloaded papers in IEEE Trans. on VLSI in 2009)
J. Sha, Z. Wang, M. Gao, and L. Li, “Multi-Gb LDPC Code Design and Implementation,” in IEEE Trans. on VLAI Systems in Feb. 2009 (Top 5 most downloaded papers in IEEE Trans. on VLSI in 2009)
P. Zhao, J. McNeely, W. Kuang, and Z. Wang, “Design of Sequential elements for Low Power Clocking Systems,” in IEEE Trans. on VLSI, in May 2011 (Top 18 most downloaded papers in IEEE Trans. on VLSI in 2011).
J. He, H. Liu, Z. Wang, and X. Huang,, “High-Speed Low-Power Viterbi Decoder Design for TCM Decoders,” in IEEE Trans. on VLSI Systems, in Apr. 2011 (Top 15 most downloaded papers in IEEE Trans. on VLSI in 2012).
