1995.04 - 1998.09 西北工业大学，电子工程专业，博士学位 1992.09－1995.03 西北工业大学，电子工程专业，硕士学位 1985.07－1989.06 西北工业大学，电子工程专业，学士学位

1999.06－2001.06 新加坡南洋理工大学电子电气学院微电子系，博士后 2001.06－2002.10 新加坡南洋理工大学无线定位中心，研究员 2002.10－2005.01 Singapore Technologies Engineering先进技术中心，高级工程师 2005.03 - 2012.12 电子科技大学微固学院微系统与芯片集成设计中心，副教授 2013.01 - 至今 电子科技大学微固学院微系统与芯片集成设计中心，教授

1. Aiwu Ruan, et al, “A bitstream readback-based automatic functional test and diagnosis method for Xilinx FPGAs“, Microelectronics Reliability (Elsevier), Vol.54, Issue 8, pp.1627-1635, 2014. 2. Aiwu Ruan, et al, “Insight into a Generic Interconnect Resource Model for Xilinx Virtex and Spartan Series FPGAs“,IEEE Transactions on Circuits and Systems II, Vol.60, No.11, 2013. 3. Aiwu Ruan, et al, “A Built-In Self-Test (BIST) System with Non-Intrusive TPG and ORA for FPGA Test and Diagnosis”, Microelectronics Reliability (Elsevier), Vol.53,Issue 3, pp.488-498, March 2013. 4. A.W. Ruan,et al, “SOC HW/SW Co-Verification Based Debugging Technique”, The International Journal for Computation and Mathematics in Electrical and Electronic Engineering, Vol.32,No.2, pp.545-555, 2013. 5. A.W. Ruan, et al, “Graph Theory for FPGA Minimum Configurations”, Journal of Semiconductors (半导体学报), Vol.32, No.11, 2011. 6. 项传银，阮爱武, “基于故障映射的FPGA互连资源故障测试与定位”, 《仪器仪表学报》,Vol.32, No.9,2011. 7. A.W. Ruan, et al, “Performance Estimation for A EDA Tool Based HW/SW Co-Verification Environment”, The International Journal for Computation and Mathematics in Electrical and Electronic Engineering, Vol.29,No.2, 2010, pp.306-316. 8. K. Shen, A.W. Ruan and B. Hu, “Design of A Control Circuit for A User Reconfigurable ROIC for IRFPA Applications”, The International Journal for Computation and Mathematics in Electrical and Electronic Engineering, Vol.29,No.2, 2010, pp.327-337. Conference Papers 1. A.W. Ruan, et al, “Debugging Methodology for A Synthesizable Testbench FPGA Emulator”, The 13th IEEE International Symposium on Integrated Circuits (ISIC 2011), Singapore, Dec.2011. 2. Haocheng Huang, Aiwu Ruan, et al, “A New Event Driven Testbench Synthesis Engine for FPGA Emulation”, The 9th IEEE International Conference on ASIC, Oct. 2011. 3. X. Cheng, A.W. Ruan,et al, “A Run-Time RTL Debugging Methodology for FPGA-based Co-Simulation”, The 8th IEEE International Conference on Communications, Circuits and Systems (ICCCAS2010), July, 2010. 4. A.W. Ruan, et al, “An Automatic Test Approach for Field Programmable Gate Array (FPGA)”, The 12th IEEE International Symposium on Integrated Circuits (ISIC 2009), Singapore, Dec.2009. 5. A.W. Ruan, et al, “Automatic Configuration Generation for A SOC Co-Verification Technology Based FPGA Functional Test System”, The 8th IEEE International Conference on ASIC, Oct. 2009. 6. A.W. Ruan, et al, “An ALU-Based Universal Architecture for FIR Filters”, The 7th IEEE International Conference on Communications, Circuits and Systems (ICCCAS2009), July, 2009. 7. A.W. Ruan, et al, “Adjustable Gain CTIA Cell with Variable Integration Time for IRFPA Applications”, The 7th IEEE International Conference on Communications, Circuits and Systems (ICCCAS2009), July, 2009. 8. A.W. Ruan, et al, “A Self-Defined Communication Protocol of Transport Layer in Hierarchy Transaction – Level Architecture for SOC Verification”, The 7th IEEE International Conference on Communications, Circuits and Systems (ICCCAS2009), July, 2009. 9. A.W. Ruan, et al, “A Parasitic Effect – Free Test Scheme for Ferroelectric Random Access Memory (FRAM)”, IEEE Circuits and Systems International Conference on Testing and Diagnosis, April, 2009. 10. A.W. Ruan, et al, “A Stream-Mode Based HW/SW Co-Emulation System for SOC Test and Verification”, IEEE Circuits and Systems International Conference on Testing and Diagnosis, April, 2009.