人工智能处理器 Deep Learning Processor

1.C. Chen, et al., “iFPNA: A Flexible and Efficient Deep Neural Network Accelerator with a Programmable Data Flow Engine in 28nm CMOS,” ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC), Dresden, 2018, pp. 170-173.

2.C. Chen, et al., “OCEAN: An On-Chip Incremental-Learning Enhanced Artificial Neural Network Processor With Multiple Gated-Recurrent-Unit Accelerators,” in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 8, no. 3, pp. 519-530, Sept. 2018.

3.C. Chen et al., “OCEAN: An on-chip incremental-learning enhanced processor with gated recurrent neural network accelerators,” ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, Leuven, 2017, pp. 259-262.

数模混合集成电路 Analog and Mixed Signal Design

1.A. Wang, C. Chen and C. R. Shi, “A 9-bit Resistor-Based All-Digital Temperature Sensor with a SAR-Quantization Embedded Differential Low-Pass Filter in 65nm CMOS Consuming 57pJ with a 2.5 us Conversion Time”, Custom Integrated Circuit Conference (CICC 2019), Austin, TX, April 2019.

2.A. Wang, C. Chen and C. R. Shi, “Design and Analysis of an Always-ON Input-Biased pA-Current Sub-nW mV-Threshold Hysteretic Comparator for Near-Zero Energy Sensing,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 9, pp. 2284-2294, Sept. 2017.

3.C. Chen, et al., “An ARMA-Model-Based NTF Estimation on Continuous-Time Delta Sigma Modulator,” in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 62, no. 8, pp. 721-725, Aug. 2015.

4.C. Chen, et al., “A low-offset calibration-free comparator with a mismatch-suppressed dynamic preamplifier,” 2014 IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne VIC, 2014, pp. 2361-2364.

5.C. Chen, et al., “An 8-bit 100-MS/s Digital-to-Skew Converter with 200-ps range for time-interleaved sampling,” 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), Boise, ID, 2012, pp. 1100-1103.

6.B. Yu, C. Chen, et al., “A 14-bit 200-MS/s time-interleaved ADC with sample-time error detection and cancelation,” IEEE Asian Solid-State Circuits Conference 2011, Jeju, 2011, pp. 349-352.

软硬件协同设计 Hardware-Software Co-design

1.C. Chen, et al., “Exploring the Programmability for Deep Learning Processors: from Architecture to Tensorization,” 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), San Francisco, CA, 2018, pp. 1-6.